It is known in digital electronics that threshold functions find many applications including parallel counters. It is also known that in static cmos circuits inverting gates are both fast and have small silicon area.
In the following + denotes logical OR, proximity denotes Logical AND, c denotes complement. A logical function with n inputs and one output, which is high if at least k of the n inputs are high, will be denoted by [n,k]. These functions are also known as threshold functions. It is also known that if the inputs to [n,k] are inverted, denoted [n,k], and the output is also inverted the resulting function is the threshold function [n,n−k+1]. In the notation this can be stated as[n,k]c=[n,n−k+1].List of Gates Referred to Herein After
GateLogic equationNAND(AB)cNOR(A + B)cOAI211((A + B)CD)cOAI22((A + B)(C + D))cAOI22(AB + CD)cAOI21(AB + C)cAOI211(AB + C + D)cOAI21((A + B)C)c
It is known that for parallel counters the threshold functions [4,1], [4,2], [4,3], and [4,4] need to be implemented. A prior art method is shown in FIG. 1. The drawback of this implementation is that none of the gates is an inverting gate. Each gate in the implementation being an AND gate or an OR gate.